The present invention relates to a method for fabricating a MOS transistor having a lightly doped drain structure capable of simplifying the fabrication and improving characteristics of the transistor.
In case of MOS transistors having a high integrity, a high electric field may occur at edge portions of a gate electrode formed, thereby causing a generation of hot carriers. These hot carriers serve to degrade an operation characteristic of MOS transistors and reduce the use life of the MOS transistors.
For eliminating such a hot carrier effect, a lightly doped drain (LDD) structure has been proposed which includes a highly doped impurity region and a lightly doped impurity region disposed adjacent to the highly doped impurity region.
FIG. 1 is a sectional view of a general n type LDD transistor.
For fabricating this n type LDD transistor, an oxide film and a polysilicon film are formed over a p type semiconductor substrate 11. These films are then patterned to form a gate oxide film 15 and a gate in a channel region. Using the gate 16 as a mask, n type impurity ions are implanted in a low concentration in the substrate to form a low concentration source/drain region 13. An oxide film is deposited over the entire exposed surface of the substrate 11 and then subjected to an anisotropic etching to form side wall spacers 17. Finally, n type impurity ions are implanted in a high concentration in the substrate 11 using the side wall spacers 17 as a mask, thereby forming a high concentration source/drain region 14.
In this LDD MOS transistor shown in FIG. 1, however, hot carriers generated are trapped in the oxide film 17 on the low concentration source/drain region 13. As a result, there is a problem that series resistance for reducing transconductance of the transistor may be modulated.
For solving such a problem, there has been proposed an inverse-T gate LDD MOS transistor wherein a gate has an inverse-T structure including a thick portion disposed at a channel region and a thin portion overlapped with a low concentration source/drain region.
FIGS. 2A to 2F are sectional views respectively illustrating a method for fabricating an LDD MOS transistor having a conventional inverse-T gate structure.
In accordance with this method, a thin oxide film 22 is formed over a silicon substrate 21, as shown in FIG. 2A. Over the oxide film 22, a thick polysilicon film 23 is coated. Another oxide film 24 is then formed over the polysilicon film 23. Thereafter, a photoresist film 25 is coated over the oxide film 24. The photoresist film 25 is then photo-etched to form a desired pattern. As a result, the oxide film 24 is exposed at its portions other than a portion disposed beneath the patterned photoresist film 25.
Using the patterned photoresist film 25 as a mask, the oxide film 24 is then etched, thereby causing the polysilicon film 23 to be partially exposed, as shown in FIG. 2B. The exposed portion of polysilicon film is then etched to a predetermined depth from its surface. As a result, the polysilicon film 23 still has its initial thickness at its portion 23A corresponding to the channel region whereas it has a reduced thickness at its portion 23B other than the portion 23A.
Thereafter, the remaining photoresist film 25 is removed, as shown in FIG. 2C. After removal of the photoresist film 25, n type impurity ions are implanted in the silicon substrate 21 so as to form low concentration n type source and drain regions 26 and 27. At this time, the oxide film 24 serves to prevent the impurity ions from being implanted in the silicon substrate 21 through the thick portion 23A of the polysilicon film 23. In other words, the impurity ions are implanted in the silicon substrate 21 only through the thin portion 23B of the polysilicon film 23.
Over the entire exposed surface of the resulting structure, another oxide film is thickly deposited, as shown in FIG. 2D. The oxide film is then subjected to an anisotropic etching to form side wall spacers 28.
Using the side wall spacers 28 as a mask, the thin polysilicon film portion 23B is etched so as to form a gate having an inverse-T structure including a leg portion corresponding to the thick polysilicon film portion 23A and a top portion corresponding to the thin polysilicon film portion 23B, as shown in FIG. 2E.
Subsequently, n type impurity ions are implanted in the silicon substrate 21 using the side wall spacers 28, the oxide film 24 and the gate 23 as a mask, thereby forming a high concentration n type source and drain regions 29 and 30, as shown in FIG. 2F.
Finally, the side wall spacers 28 are removed. Thus an LDD MOS transistor is obtained which includes the inverse-T gate 23 overlapped at its top portion 23B with the low concentration source and drain regions 26 and 27.
The above-mentioned method for fabricating the conventional LDD MOS transistor having the inverse-T gate involves a difficulty to accurately control the step of etching the polysilicon film to form the inverse-T gate. As a result, it is difficult to fabricate a desired transistor.
FIGS. 3A to 3F illustrate a method for fabricating an LDD MOS transistor having an improved inverse-T gate, respectively.
In accordance with this method, a p type silicon substrate 41 is subjected to a well-known field oxidation to form an isolation field oxide film 42, as shown in FIG. 3A. A gate oxide film 44 is then grown over an active region 43 of the p type silicon substrate 41. Over the gate oxide film 44, a first polysilicon film 45 is then deposited. A low temperature oxide (LTO) film 46 is deposited over the first polysilicon film 45 and then etched to form an opening 47.
Over the entire exposed surface of the resulting structure, a nitride film is then etched, as shown in FIG. 3B. The nitride film is subjected to an anisotropic etching to form spacers 48 at respective side walls of the LTO film 46. Using the spacers 48 as a mask, impurity ions are implanted in the silicon substrate 41 through the opening 47, thereby forming a p type channel region 49.
Thereafter, a selected deposition of a second polysilicon film 50 is carried out for filling the opening 47 with the second polysilicon film 50, as shown in FIG. 3C. The second polysilicon film 50 filling the opening 47 constitutes a leg portion of an inverse-T gate to be obtained.
Using the second polysilicon film 50 and the spacer 48 as a mask, the LTO film 46 is completely removed, as shown in FIG. 3D. As a result, the first polysilicon film is exposed at its portion other than its portions beneath the spacers 48 and the second polysilicon film 50. Then, n type impurity ions are implanted in a high concentration in the silicon substrate 41 using the second polysilicon film 50 and the spacers 48 as a mask, thereby forming high concentration source and drain regions 51 and 52 in both sides of the channel region 49, respectively.
After the ion implantation, the exposed portion of first polysilicon film 45 is etched using the spacers 48 as a mask, as shown in FIG. 3E. At this time, the remaining first polysilicon film 45 constitutes a top portion of an inverse-T gate to be obtained. Thus an inverse-T gate 53 is obtained which has a top portion constituted by the first polysilicon film 45 and a leg portion constituted by the second polysilicon film 50.
Thereafter, the side wall spacers 48 are removed, as shown in FIG. 3F. Finally, n type impurity ions are implanted in a low concentration in the silicon substrate 41, thereby forming low concentration source and drain regions 54 and 55 between the channel region 49 and the high concentration source region 51 and between the channel region 49 and the high concentration drain region 52, respectively.
Thus a MOS transistor is obtained which has an LDD structure including the inverse-T gate 53 constituted by the first polysilicon film 45 and the second polysilicon film 50, the low concentration source and drain regions 54 and 55, and the high concentration source and drain regions 51 and 52.
However, since the gate oxide film is grown at the early stage of the fabrication in accordance with this method, it may be damaged at subsequent etching steps. As a result, the reliability may be degraded. This method also involves a problem that the resistance of the gate itself is increased because the inverse-T gate is constituted by two polysilicon films.